| 作成者 |
|
|
|
|
|
|
|
|
|
|
|
|
|
| 本文言語 |
|
| 発行日 |
|
| 収録物名 |
|
| 出版タイプ |
|
| アクセス権 |
|
| 関連DOI |
|
| 関連URI |
|
| 関連情報 |
|
| 概要 |
Advances in semiconductor technology and increased reusability of IPs enable embedded system designers to develop Systems-On-Chip (SOCs) which are customized for a specific application (or application... domain). Specifically, customization of processor architecture and memories is enabled, which allows efficient implementation of SOCs. Up to now, a number of research efforts on processor customization have been made in both industry and academia, where the instruction set and the datapath configuration are prime design parameters. In this paper we demonstrate that the datapath bitwidth has a large impact on system performance, chip area, and energy consumption, and then propose a framework and tools for datapath bitwidth optimization. Two case studies are presented to prove the effectiveness of the optimization.続きを見る
|
Mendeley出力
tomiyama02_1