<会議発表論文>
Limits of Parallelism on Thread-Level Speculative Parallel Processing Architecture

作成者
本文言語
出版者
発行日
収録物名
出版タイプ
アクセス権
関連DOI
関連URI
関連情報
概要 Two fundamental restrictions that limit the amount of instructionlevel parallelism extracted from sequential programs are control flow and data flow. TLSP (Thread-Level Speculative Parallel processing...) architecture gains high parallelism using three techniques (speculation with branch prediction, control dependence analysis, executing multiple flows of control) which relax constraints due to control dependences. In this paper, we evaluate the effects of three techniques (memory disambiguation, renaming, value prediction) which relax constraints due to data dependences on TLSP architecture. We have two major results. First, parallelism for TLSP architecture is restricted by enormous output and anti dependences on memory. Second, value prediciton has large effects on TLSP architecture.続きを見る

本文ファイル

pdf metsugi02_2 pdf 85.5 KB 229  

詳細

レコードID
査読有無
注記
タイプ
登録日 2009.04.22
更新日 2017.01.25

この資料を見た人はこんな資料も見ています