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A Phase Frequency Detector Constructed with Dynamic CMOS Gates for Low Power PLL

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概要 To reduce power dissipation of LSI drastically, it is very effective to lower supply voltage, for example from 5V to 3V or 3V to 1.5V, because power dissipation is proportional to the square of supply... voltage. However, reduction of supply voltage results in the increase of propagation delay of the constituent gates. In case of PFD (Phase Frequency Detector) which is one of the components of PLL (Phase Locked Loop), increase of the propagation delay deteriorates its phase detecting characteristics and therefore pull-in characteristics of the PLL. One of the solutions to this problem is the construction of PFD with dynamic CMOS gates as we proposed in our earlier paper. In this paper, we propose a systematic and straightforward method to construct PFD with dynamic CMOS gates and clarify the effect of the dynamic structure on PFD and PLL performance.続きを見る

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登録日 2015.01.23
更新日 2020.11.02

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