| 作成者 |
|
|
|
| 本文言語 |
|
| 発行日 |
|
| 収録物名 |
|
| 収録物名 |
|
| 開始ページ |
|
| 終了ページ |
|
| 出版タイプ |
|
| アクセス権 |
|
| 関連DOI |
|
|
|
|
|
| 関連URI |
|
|
|
|
|
| 関連情報 |
|
|
|
|
|
| 概要 |
The advance in semiconductor technologies presents the serious problem of parameter variations. The affect threshold voltage of transistors and thus circuit delay also has variations. Recently, variab...le latency adders and long latency adders are proposed to manage the variation problem. Unfortunately, replacement of variation-affected adder with the long latency ones has severe impact on processor performance. In order to maintain performance, this paper proposes an instruction scheduling technique considering instruction criticality. By issuing and executing only uncritical instructions in the long latency ALU, we can maintain processor performance. From detailed simulations, we find that the proposed scheduling technique improves processor performance by 12.5% on average over the conventional scheduling, and performance degradation from a variation-free processor is only 4.0% on average when 2 of 4 ALU’s are affected by variations.続きを見る
|
Mendeley出力
