Design and Implementation of Soft Error Resilient 14T SRAM Cell - 九大コレクション | 九州大学附属図書館

＜学術雑誌論文＞
Design and Implementation of Soft Error Resilient 14T SRAM Cell

作成者	作成者名 Sahi, Nagma 所属機関所属機関名 Department of Electronics and Communication Engineering, National Institute of Technology Delhi
	作成者名 Bharti, Manisha 所属機関所属機関名 Department of Electronics and Communication Engineering, National Institute of Technology Delhi
	作成者名 Ms. Ashima Sharma 所属機関所属機関名 Department of Electronics and Communication Engineering, National Institute of Technology Delhi
本文言語	英語
出版者	Interdisciplinary Graduate School of Engineering Sciences, Kyushu University, Japan
出版者	九州大学大学院総合理工学府
発行日	2023-06
収録物名	Evergreen
巻	10
号	2
開始ページ	1100
終了ページ	1105
出版タイプ	Version of Record
アクセス権	open access
Crossref DOI	https://doi.org/10.5109/6793669
権利関係	Creative Commons Attribution-NonCommercial 4.0 International
概要	As part of this effort, the CC14T, cross-coupled memory cell with 14 transistor architecture has been proposed, with defence against soft errors such as single event upsets (SEUs). The CC14T cell is p...resented, which consists of 4 cross-coupled input-split inverters and four access transistors. The cell achieves optimum SEU tolerance owing to a feedback structure among its internal nodes. It has been implemented and analyzed under 40nm regime, and the findings demonstrate that it consumes 43.01 nW of power with supply voltage of 0.8V and takes 6.64 percent and 15.5 percent less time to write and read than a typical 6T SRAM cell. As compared to the other cell considered, the CC14T cell has a faster write access time and higher stability due to its soft error resistance.続きを見る
目次	1.Introduction 2.Previous Memory Cells 3.Proposed CC14T Cell 4.Observation and Evaluation Results 5.Conclusion

本文ファイル

ファイル	ファイルタイプ	利用条件	サイズ	閲覧回数	説明
p1100-1105	pdf	なし	1.07 MB	772

詳細

PISSN	2189-0420
EISSN	2432-5953
レコードID	6793669
査読有無	査読有
主題	Single Event Upset
	Soft Error
	SRAM
登録日	2023.07.10
更新日	2026.03.27