Mendeley出力
＜学術雑誌論文＞
Performance Analysis of Pulse Triggered Flip-Flop
| 作成者 | |
|---|---|
| 本文言語 | |
| 出版者 | |
| 発行日 | |
| 収録物名 | |
| 巻 | |
| 号 | |
| 開始ページ | |
| 終了ページ | |
| 出版タイプ | |
| アクセス権 | |
| Crossref DOI | |
| 権利関係 | |
| 概要 | The power efficiency and speed are two main concerns in any digital as well as analog circuit design. In this work, we analyze the pulse-triggered flip-flop (PTFF). In PTFF have two main stages, the p...ulse generator (PG) and the latch circuitry. We have utilized PG that has four transistors which is less than the number of transistors comparison to the previously used PGs. The design has been implemented on Cadence Virtuoso using 22nm CMOS cell library. The various parameters like data-to-output (D-to-Q) delay, leakage power and power-delay product (PDP) are being compared with existing flip-flop circuits like master-slave flip-flop (MSFF), DFF and conventional PTFF. The modified PTFF shows 24.3% improvement in D-to-Q delay and 18.1% improvement in PDP as contrast to the conventional PTFF.続きを見る |
| 目次 | 1.Introduction 2.Modified pulse triggered flip-flop 3.Implementation and experimentalevaluation 4.Conclusion |
本文ファイル
| ファイル | ファイルタイプ | サイズ | 閲覧回数 | 説明 |
|---|---|---|---|---|
p1010-1016
|
1.43 MB | 459 |
詳細
| PISSN | |
|---|---|
| EISSN | |
| レコードID | |
| 査読有無 | |
| 主題 | |
| 登録日 | 2023.07.10 |
| 更新日 | 2024.02.21 |