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近年のマイクロプロセッサには処理性能を維持しつつ消費電力を削減することが求められている． 我々はプログラム実行中のクリティカルパス情報で低速・高速な演算器を使い分ける省電力アーキテ クチャを提案している．本稿では，クリティカルパス予測器を更新する際に分岐予測ミス情報，キャッ シュミス中に実行される命令の情報などを利用することを提案する．また，プログラム実行中のトレー ス情報を用いて測定したクリティ...カルパス予測器の予測精度について報告する．
Recently, microprocessors are required to reduce energy consumption maintaining its computation performance. Microprocessors we are proposing have two types of functional units distinguished in terms of their execution latency and power consumption. Only critical instructions are executed on power-hungry functional units, and thus the total energy consumption can be reduced without severe performance loss. In this paper, we propose new critical path detection criteria that utilize information of miss branch predicted instruction instruction executed during cache miss, and so on. Those criteria make the information updating critical path predictor. We evaluate critical path prediction accuracy comparing with the trace information executing program.show more
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chiyonobu06_2