Limits of Parallelism on Thread-Level Speculative Parallel Processing Architecture - Collections | Kyushu University Library

＜conference paper＞
Limits of Parallelism on Thread-Level Speculative Parallel Processing Architecture

Creator	Creator Name Metsugi, Katsuhiko 目次, 勝彦 Affiliation Affiliation Name Department of Informatics, Kyushu University 九州大学大学院システム情報科学研究院
Creator	Author PID K000171 Creator Name Murakami, Kazuaki 村上, 和彰 Affiliation Affiliation Name Department of Informatics, Kyushu University 九州大学大学院システム情報科学研究院
Language	English
Publisher	International Workshop on Informationons and Electrical Engineering
Date	2002-05
Source Title	SLRC Papers Database
Publication Type	Accepted Manuscript
Access Rights	open access
Related DOI	http://www.c.csce.kyushu-u.ac.jp/SOC/index_j.html
Related URI	http://www.c.csce.kyushu-u.ac.jp/SOC/index_j.html
Relation	http://www.c.csce.kyushu-u.ac.jp/SOC/index_j.html
Abstract	Two fundamental restrictions that limit the amount of instructionlevel parallelism extracted from sequential programs are control flow and data flow. TLSP (Thread-Level Speculative Parallel processing...) architecture gains high parallelism using three techniques (speculation with branch prediction, control dependence analysis, executing multiple flows of control) which relax constraints due to control dependences. In this paper, we evaluate the effects of three techniques (memory disambiguation, renaming, value prediction) which relax constraints due to data dependences on TLSP architecture. We have two major results. First, parallelism for TLSP architecture is restricted by enormous output and anti dependences on memory. Second, value prediciton has large effects on TLSP architecture.show more

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Record ID	3713
Peer-Reviewed	Unrefereed
Notes	International Workshop on Informationons and Electrical Engineering (IWIE2002)
Type	会議発表論文
Created Date	2009.04.22
Modified Date	2017.01.25