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＜conference paper＞
A Power Minimization Technique for Arithmetic Circuits by Cell Selection

Creator	Creator Name Muroyama, Masanori 室山, 真徳 Affiliation Affiliation Name Department of Computer Science and Communication Engineering Graduate School of Information Science and Electrical Engineering Kyushu University 九州大学システム情報科学研究院情報工学部門
	Author PID K002825 Creator Name Ishihara, Tohru 石原, 亨 Affiliation Affiliation Name VSLI Design and Education Center(VDEC) University of Tokyo 東京大学大学院大規模集積システム設計教育研究センター
	Creator Name Hyodo, Akihiko 兵頭, 章彦 Affiliation Affiliation Name Department of Computer Science and Communication Engineering Graduate School of Information Science and Electrical Engineering Kyushu University 九州大学システム情報科学研究院情報工学部門
	Author PID K000217 Creator Name Yasuura, Hiroto 安浦, 寛人 Affiliation Affiliation Name Department of Computer Science and Communication Engineering Graduate School of Information Science and Electrical Engineering Kyushu University 九州大学システム情報科学研究院情報工学部門
Language	English
Publisher	7th Asia South Pacific Design Automation Conference and 15th International Conference on VLSI Design
Date	2002-01
Source Title	7th Asia South Pacific Design Automation Conference and 15th International Conference on VLSI Design (ASP-DAC2002)
Source Title	SLRC Papers Database
Publication Type	Accepted Manuscript
Access Rights	open access
Related DOI	7th Asia South Pacific Design Automation Conference and 15th International Conference on VLSI Design (ASP-DAC2002) \|\| \|\|
Related DOI	http://www.c.csce.kyushu-u.ac.jp/SOC/index_j.html
Related URI	7th Asia South Pacific Design Automation Conference and 15th International Conference on VLSI Design (ASP-DAC2002) \|\| \|\|
Related URI	http://www.c.csce.kyushu-u.ac.jp/SOC/index_j.html
Relation	7th Asia South Pacific Design Automation Conference and 15th International Conference on VLSI Design (ASP-DAC2002) \|\| \|\|
Relation	http://www.c.csce.kyushu-u.ac.jp/SOC/index_j.html
Abstract	As a basic cell of arithmetic circuits, a one-bit full adder and a counter are usually used. Minimizing power consumption of these components is a key issue for low-power circuit design. This paper pr...oposes a new design method, in which basic cells are selected from a set of circuits with different structures (symmetrical and asymmetrical) and connections to their terminals are exchanged, according to input-patterns to minimize power consumption. Experimental results for a parallel multiplier demonstrate average 30% power reduction.show more

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Record ID	3534
Peer-Reviewed	Unrefereed
Subject Terms	low power
	cell based design
	input patterns
	arithmetic circuits
Type	会議発表論文
Created Date	2009.04.22
Modified Date	2017.01.24