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A design of clock generation PLL which improves the jitter performance and reduces the chip area is described. To reduce the VCO jitter, DC voltage regulator for stabilizing the supply voltage of PLL ...and a design method of optimum PFD characteristics are proposed. Utilizing the proposed design method, the jitter of the PLL is reduced to 40psec at 320MHz operating frequency under the noisy supply voltage condition. For the reduction of chip area, a filter circuit with variable capacitance are realized by a buffer and a small fixed capacitance. A new VCO bias circuit is also proposed to realize the linear VCO characteristics. The effective performance of the proposed filter and bias circuit is confirmed by SPICE simulation.続きを見る
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Mendeley出力
