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＜conference paper＞
A Combined Analytical and Simulation-Based Model for Performance Evaluation of a Reconfigurable Instruction Set Processor

Creator
Creator Name
Mehdipour, Farhad
Affiliation
Affiliation Name
Faculty of Information Science and Electrical Engineering, Kyushu University
Creator Name
Noori, Hamid
Affiliation
Affiliation Name
Institute of Systems, Information Technologies and Nanotechnologies
Creator Name
Javadi, Bahman
Affiliation
Affiliation Name
Computer Engineering and IT Department, Amirkabir University of Technology
Author PID
K002790
Creator Name
Honda, Hiroaki
本田, 宏明
ホンダ, ヒロアキ
Affiliation
Affiliation Name
Computer Engineering and IT Department, Amirkabir University of Technology
九州先端科学技術研究所
Author PID
K002613
Creator Name
Inoue, Koji
井上, 弘士
イノウエ, コウジ
Affiliation
Affiliation Name
Department of Informatics, Kyushu University
九州大学システム情報科学研究院
Author PID
K000171
Creator Name
Murakami, Kazuaki
村上, 和彰
ムラカミ, カズアキ
Affiliation
Affiliation Name
Department of Informatics, Kyushu University
九州大学システム情報科学研究院
Language
English
Date
2009-01-21
Source Title
Asia and South-Pacific Design Automation Conference
Source Title
SLRC Papers Database
Vol
14
First Page
564
Last Page
569
Publication Type
Accepted Manuscript
Access Rights
open access
Related DOI
Asia and South-Pacific Design Automation Conference || 14 || p564-569
アジア南太平洋設計自動化会議 || 14 || p564-569
http://www.slrc.kyushu-u.ac.jp/index-j.html
Related URI
Asia and South-Pacific Design Automation Conference || 14 || p564-569
アジア南太平洋設計自動化会議 || 14 || p564-569
http://www.slrc.kyushu-u.ac.jp/index-j.html
Relation
Asia and South-Pacific Design Automation Conference || 14 || p564-569
アジア南太平洋設計自動化会議 || 14 || p564-569
http://www.slrc.kyushu-u.ac.jp/index-j.html
Abstract Performance evaluation is a serious challenge in designing or optimizing reconfigurable instruction set processors. The conventional approaches based on synthesis and simulations are very time consumi...ng and need a considerable design effort. A combined analytical and simulation-based model (CAnSO.) is proposed and validated for performance evaluation of a typical reconfigurable instruction set processor. The proposed model consists of an analytical core that incorporates statistics gathered from cycle-accurate simulation to make a reasonable evaluation and provide a valuable insight. Compared to cycle-accurate simulation results, CAnSO proves almost 2% variation in the speedup measurement.show more

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Details

Record ID
13246
Peer-Reviewed
Refereed
Notes
第14回アジア南太平洋設計自動化会議 (ASP-DAC 2009) : 2009年1月19日(月)～22日(木) : パシフィコ横浜, 横浜市
Type
会議発表論文
Created Date 2009.04.22
Modified Date 2020.11.27

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