<technical report>
Pulse Generation Analysis for SER Estimation Targeted to Cell-based Design.

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Abstract スキャンチェーンを悪用して,暗号LSI上で扱われる秘密情報を特定するスキャンベース攻撃の危険性が指摘されている.スキャンベース攻撃に対する防御法には様々な手法が存在する.回路設計時には,これらの防御法を適用した回路のセキュリティを定量的に評価し,防御法を選択する必要がある.しかしながら,スキャンベース攻撃に対する回路の定量的なセキュリティ評価については,あまり議論されていない.そこで本稿では,スキ...ャンベース攻撃に対する回路のセキュリティ評価手法を提案する.提案手法では,攻撃者が取得できる取得情報と攻撃者が特定したい秘密情報との相互情報量を指標として評価を行う.回路構成の異なるDES 回路を例に提案評価手法を用いてセキュリティを評価し,回路構成によって回路のセキュリティが異なることを定量的に示す.
The charge deposition that results from a neutron strikes to a transistor alter the memory state or the logic state of output at a gate is called soft error. To design logic circuits of tolerance to soft error, it is necessary to evaluate the soft error tolerance of a gate. SER(Soft Error Rate) is a measure of soft error tolerance at a gate. If the characteristics of the pulse generated by a neutron strike are characterized beforehand for every library gate, it becomes possible to obtain SER of the circuit without circuit simulation for all the gates. To characterize the pulse width and the pulse generation probability, this paper describes a pulse generation analysis method using HSPICE simulation to obtain the pulse generation probability at a gate by a pulse width. The experimental results that evaluate the approximate accuracy of our method show our approximation error is very small compared to HSPICE. When the number of samples that results from HSPICE simulation was little, our approximation error was also small as well as the samples were a lot of numbers, and the difference of SER derived from variation of the number of samples was very little.
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Created Date 2010.05.11
Modified Date 2022.01.24

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