作成者 |
|
|
|
本文言語 |
|
出版者 |
|
発行日 |
|
収録物名 |
|
収録物名 |
|
開始ページ |
|
終了ページ |
|
出版タイプ |
|
アクセス権 |
|
関連DOI |
|
|
関連URI |
|
|
関連情報 |
|
|
概要 |
Datapath width optimization is very effective for reducing the area of a custom-made embedded system. The trivial way of optimization is to iteratively customize, evaluate, and redesign a system to re...ach near an optimal value. The resulting effect is a long design time. In this paper, we introduce an effective scheme that accelerates design. A system-level pruning of design exploration space speeds up the optimization process. Through a single-pass simulation for a reference customization and a model for estimating and evaluating the system’s performance, pruning of design space is achieved. Experimental results show that a substantial reduction in design time is possible.続きを見る
|