| 作成者 |
|
|
|
| 本文言語 |
|
| 発行日 |
|
| 収録物名 |
|
| 収録物名 |
|
| 巻 |
|
| 出版タイプ |
|
| アクセス権 |
|
| 関連DOI |
|
|
|
| 関連URI |
|
|
|
| 関連情報 |
|
|
|
| 概要 |
It is difficult for LUT-based FPGA technology mapping to generate a power-minimal K-input LUT network with minimum depth at one time because a problem for power-minimization was shown to be NP-hard[5].... A problem for area-minimization is also NP-hard, and area-aware algorithms[7][8][9][10] recover area after generating a depthminimum network. On the other hand, existing poweraware algorithms[11][12][13][14] finish with generating a depthminimum network whose power is small. There might be room for power improvement for the generated network. This paper presents a post-processing to minimize power under depth constraint for LUT-based FPGA technology mapping. The proposed algorithm is a power-aware application of Cut Resubstitution[6] which is a post-processing to minimize area under depth constraint. Experimental results show that a simple depth-minimum mapper followed by the proposed algorithm generates networks whose total switching activity is 21% smaller and dynamic power is 10% smaller than that generated by Emap[13] for the input size of LUT K = 4. The results also show that total switching activity is associated with dynamic power. The proposed method generated networks whose total switching activity is 24%, 27% smaller than that generated by Emap on average for K = 5, 6, respectively. The proposed algorithm runs in practical run-time for all the case.続きを見る
|
Mendeley出力
