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This paper describes a CMOS 1st-order delay-line DPLL in l.2μm technology for clock regeneration. We have employed a parallel-architecture PC (Phase Comparator) to improve the speed and a DCO (Digital...ly Controlled Oscillator) without timing hazard. And we have also laid it out in 1.2μm CMOS, and simulated its performance by SPICE as well as logic simulation. Results show that the DPLL operates up to 60MHz, and that lock-in ranges are +5/-5% for regular" 10" input and +5/-5% for 2^13-1 PRBS (Pseudo-Random Bit Sequence) input, respectively.続きを見る
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Mendeley出力
