<会議発表論文>
Power-Performance Trade-off of a Dependable Multicore Processor

作成者
本文言語
発行日
雑誌名
雑誌名
開始ページ
終了ページ
出版タイプ
アクセス権
概要 As deep submicron technologies are advanced, new challenges, such as power consumption and soft errors, are emerging. A naive technique, which utilizes emerging multicore processors and relies upon th...read-level redundancy to detect soft errors, is power hungry. Another technique, which relies upon instruction-level redundancy, diminishes computing performance seriously. This paper investigates trade-off between power and performance of a dependable multicore processor, which is named multiple clustered core processor (MCCP). It is proposed to hybrid thread- and instruction-level redundancy to achieve both large power efficiency and small performance loss. Detailed simulations show that the MCCP exploiting the hybrid technique improves power efficiency in energy-delay product by 13% when it is compared with the one exploiting the naive thread-level technique.続きを見る

本文情報を非表示

sato07_9 pdf 279 KB 74  

詳細

レコードID
査読有無
関連情報
主題
注記
タイプ
登録日 2009.04.22
更新日 2017.07.26