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Reduction of Coupling Effects by Optimizing the 3-D Configuration of the Routing Grid

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概要 In this brief, we propose a new physical design technique for a subquarter micrometer system-on-a-chip (SoC). By optimizing the individual layer’s routing grid space, coupling effects such as crosstal...k noise, crosstalk-induced delay variations, and coupling power consumption are almost eliminated with little runtime penalty. Experiments are performed on the design of an image processing circuit using a subquarter micron CMOS process with multilayer interconnects. Simply by employing our proposed technique, the maximum delay and the power consumption can be decreased simultaneously by up to 15% and 10%, respectively, without any other process improvements.続きを見る

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登録日 2009.04.22
更新日 2017.03.09