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Routing Methodology for Minimizing lnterconnect Energy Dissipation

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概要 In this paper, we propose a new physical design technique for sub-quarter micron system-on-a-chip (SoC). By optimizing the routing grid configuration for the automatic place and route methodology, cou...pling effects such as crosstalk noise and coupled energy dissipation are almost eliminated with only a small cost to the runtime. Experiments are performed on the design of an image processing circuit using a sub-quarter micron CMOS process with multi-layered interconnects. Simply by employing our proposed technique, net switching energy dissipation can be reduced by about 10% maximum without any area penalty. This significant energy reduction greatly accelerates the performance of SoCs.続きを見る

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登録日 2009.04.22
更新日 2017.03.02

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