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Datapath width optimization is very effective for designing a custom-made processor system with low cost and less power/energy consumption. However, to determine an optimal value of datapath width, de...signers need to iteratively work on a number of customizations which results in a long design time. In order to reduce design time, we propose an efficient scheme for reducing the design exploration space for the optimization. Through a single-pass simulation for a reference customization and a model for estimating and evaluating performance, reduction in design exploration space can be achieved. Experimental results show that substantial reduction in design exploration space is possible.続きを見る
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