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Optimization of test accesses with a combined BIST and external test scheme

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概要 External pins for test are precious hardware resources because the number of them are strongly restricted. In this paper, an optimization method of test accesses with a combined BIST and external test... (CBET) scheme is proposed. The method can minimizes test application time and eliminate the wasteful usage of external pins considering the trade-off between test application time and the number of external pins. Our ideas consist of two parts. One is to determine the optimum groups each of which consists of cores to simultaneously share mechanisms for external test. The other is to determine the optimum bandwidth of external input and output for external test. The ideas are basically used for the purpose of eliminating the wasteful external pin usage. The ideas make external test part to be under full bandwidth of external pins under consideration of the trade-off between test application time and the number of external pins. This is achieved only with CBET scheme because CBET permits test sets for both BIST and external test to be elastic. Taking test bus architecture for instance, a formulation for minimization of test application time and experimental results are shown. Experimental results shows that our optimization can achieve a 51.9% reduction of test application time of conventional test scheduling and our proposals are surely very effective to reduce test application time of SOC.続きを見る

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登録日 2009.04.22
更新日 2017.01.24