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＜journal article＞
Improving Performance and Energy Saving in a Reconfigurable Processor via Accelerating Control Data Flow Graphs

Creator
Creator Name
Mehdipour, Farhad
Affiliation
Affiliation Name
Computing and Communication Center, Kyushu University
Creator Name
Noori, Hamid
Affiliation
Affiliation Name
Department of Informatics, Kyushu University
Creator Name
Zamani, Morteza Saheb
Affiliation
Affiliation Name
Department of IT and Computer Engineering, Amirkabir University of Technology
Author PID
K002613
Creator Name
Inoue, Koji
井上, 弘士
イノウエ, コウジ
Affiliation
Affiliation Name
Department of Informatics, Kyushu University
九州大学システム情報科学研究院
Author PID
K000171
Creator Name
Murakami, Kazuaki
村上, 和彰
ムラカミ, カズアキ
Affiliation
Affiliation Name
Department of Informatics, Kyushu University
九州大学システム情報科学研究院
Language
English
Publisher
電子情報通信学会
IEICE
Date
2007-12-01
Source Title
IEICE Transactions on Information and Systems
Source Title
SLRC Papers Database
Vol
E90-D
Issue
12
First Page
1956
Last Page
1966
Publication Type
Accepted Manuscript
Access Rights
open access
Related DOI
Related DOI
IEICE Transactions on Information and Systems || E90-D(12) || p1956-1966
Related URI
IEICE Transactions on Information and Systems || E90-D(12) || p1956-1966
Related URI
isIdenticalTo
http://search.ieice.org/bin/summary.php?id=e90-d_12_1956&category=D&year=2007&lang=E&abst=
Related HDL
Relation
IEICE Transactions on Information and Systems || E90-D(12) || p1956-1966
Abstract Extracting frequently executed (hot) portions of the application and executing their corresponding data flow graph (DFG) on the hardware accelerator brings about more speedup and energy saving for emb...edded systems comprising a base processor integrated with a tightly coupled accelerator. Extending DFGs to support control instructions and using Control DFGs (CDFGs) instead of DFGs results in more coverage of application code portion are being accelerated hence, more speedup and energy saving. In this paper, motivations for extending DFGs to CDFGs and handling control instructions are introduced. In addition, basic requirements for an accelerator with conditional execution support are proposed. Then, two algorithms are presented for temporal partitioning of CDFGs considering the target accelerator architectural constraints. To demonstrate effectiveness of the proposed ideas, they are applied to the accelerator of a reconfigurable processor called AMBER. Experimental results approve the remarkable effectiveness of covering control instructions and using CDFGs versus DFGs in the aspects of performance and energy reduction.show more

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Details

Record ID
8697
Peer-Reviewed
Refereed
Related URI
http://search.ieice.org/bin/summary.php?id=e90-d_12_1956&category=D&year=2007&lang=E&abst=
Subject Terms
reconfigurable accelerator
conditional execution
control data flow graph
temporal partitioning
reconfigurable processor
ISSN
0916-8532
Type
学術雑誌論文
Created Date 2009.04.22
Modified Date 2020.11.02

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