Reducing Dynamic Power and Leakage Power for Embedded Systems - Collections | Kyushu University Library

＜conference paper＞
Reducing Dynamic Power and Leakage Power for Embedded Systems

Creator	Creator Name Cao, Yun 曹, ユンソウ, ユン Affiliation Affiliation Name Department of Computer Science and Communication Engineering, Kyushu University 九州大学大学院システム情報科学研究院
Creator	Author PID K000217 Creator Name Yasuura, Hiroto 安浦, 寛人ヤスウラ, ヒロト Affiliation Affiliation Name Department of Computer Science and Communication Engineering, Kyushu University 九州大学大学院システム情報科学研究院
Language	English
Publisher	IEEE
Date	2002-09
Source Title	In Proc. of the 15th Annual IEEE International ASIC/SOC Conference
Source Title	SLRC Papers Database
First Page	291
Last Page	295
Publication Type	Accepted Manuscript
Access Rights	open access
Related DOI	In Proc. of the 15th Annual IEEE International ASIC/SOC Conference \|\| \|\| p291-295
Related DOI	http://www.c.csce.kyushu-u.ac.jp/SOC/index_j.html
Related URI	In Proc. of the 15th Annual IEEE International ASIC/SOC Conference \|\| \|\| p291-295
Related URI	http://www.c.csce.kyushu-u.ac.jp/SOC/index_j.html
Relation	In Proc. of the 15th Annual IEEE International ASIC/SOC Conference \|\| \|\| p291-295
Relation	http://www.c.csce.kyushu-u.ac.jp/SOC/index_j.html
Abstract	This paper presents a system-level technique for embedded processor-based systems targeting both dynamic power and leakage power reduction using datapath width optimization. By means of tuning the des...ign parameter, datapath width tailored to a given application requirements, the processors and memories are optimized resulting in significant power reduction, not only for dynamic power but also for leakage power. In our experiments for several real embedded applications, power reduction without performance penalty is reported range from about 14.5% to 59.2% of dynamic power, and 21.5% to 66.2% of leakage power.show more

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Details

Record ID	5843
Peer-Reviewed	Unrefereed
NCID	BA66503265
Type	会議発表論文
Created Date	2009.04.22
Modified Date	2020.10.13