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A Digital Matched Filter (DMF) is an essential device for Direct- Sequence Spread-Spectrum (DS-SS) communication systems. Reducing the power consumption of a DMF is especially critical for battery-pow...ered terminals. The reception registers and the correlation-calculating unit dissipate the majority of the power in a DMF. In this paper we discuss this problem and propose a lowpower architectural approach to a DMF. The total switching activity factor and the switched capacitance are reduced. As a result of power analysis at the gate level, the implementation of the proposed architecture in a standard 0.18-$ mu $m CMOS technology achieved a reduction in the power consumption of more than 70 %.続きを見る
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Mendeley出力
