An Efficient Exploration Scheme for Datapath Width Optimization of Embedded Processor Systems - Collections | Kyushu University Library

＜conference paper＞
An Efficient Exploration Scheme for Datapath Width Optimization of Embedded Processor Systems

Creator	Creator Name Mesbah, Uddin M. メスバ, ウッディン Affiliation Affiliation Name Department of Computer Science and Communication Engineering, Graduate School of Information Science and Electrical Engineering, Kyushu University
	Creator Name Cao, Yun 曹, ユンソウ, ユン Affiliation Affiliation Name Department of Computer Science and Communication Engineering, Graduate School of Information Science and Electrical Engineering, Kyushu University 九州大学大学院システム情報科学府
	Author PID K000217 Creator Name Yasuura, Hiroto 安浦, 寛人 Affiliation Affiliation Name Department of Computer Science and Communication Engineering, Graduate School of Information Science and Electrical Engineering, Kyushu University 九州大学大学院システム情報科学府
Language	English
Publisher	電子情報通信学会VLD研究会
Date	2002-03
Source Title	IEICE Technical Report
Source Title	SLRC Papers Database
First Page	10
Last Page	16
Publication Type	Accepted Manuscript
Access Rights	open access
Related DOI	IEICE Technical Report\|\|VLD2001(150), ICD2001(225)\|\| p10-16
Related DOI	http://www.c.csce.kyushu-u.ac.jp/SOC/index_j.html
Related URI	IEICE Technical Report\|\|VLD2001(150), ICD2001(225)\|\| p10-16
Related URI	http://www.c.csce.kyushu-u.ac.jp/SOC/index_j.html
Relation	IEICE Technical Report\|\|VLD2001(150), ICD2001(225)\|\| p10-16
Relation	http://www.c.csce.kyushu-u.ac.jp/SOC/index_j.html
Abstract	Datapath width optimization is very effective for designing a custom-made processor system with low cost and less power/energy consumption. However, to determine an optimal value of datapath width, de...signers need to iteratively work on a number of customizations which results in a long design time. In order to reduce design time, we propose an efficient scheme for reducing the design exploration space for the optimization. Through a single-pass simulation for a reference customization and a model for estimating and evaluating performance, reduction in design exploration space can be achieved. Experimental results show that substantial reduction in design exploration space is possible.show more

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Record ID	3611
Peer-Reviewed	Unrefereed
Subject Terms	Performance
	cost
	datapath width
	optimization technique
ISSN	0913-5685
Type	会議発表論文
Created Date	2009.04.22
Modified Date	2023.11.27