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＜conference paper＞
An Accelerator Based on Single-Flex Quantum Circuits for a High-Performance Reconfigurable Computer

Creator
Creator Name
Mehdipour, Farhad
Affiliation
Affiliation Name
Graduate School of Information Science and Electrical Engineering, Department of Informatics, Kyushu University
Creator Name
Honda, Hiroaki
本田, 宏明
ホンダ, ヒロアキ
Affiliation
Affiliation Name
Institute of Systems, Information Technologies and Nanotechnologies
九州先端科学技術研究所
Author PID
K005116
Creator Name
Kataoka, Hiroshi
片岡, 広志
カタオカ, ヒロシ
Affiliation
Affiliation Name
Graduate School of Information Science and Electrical Engineering, Department of Informatics, Kyushu University
九州大学大学院システム情報科学研究院
Author PID
K002613
Creator Name
Inoue, Koji
井上, 弘士
イノウエ, コウジ
Affiliation
Affiliation Name
Graduate School of Information Science and Electrical Engineering, Department of Informatics, Kyushu University
九州大学大学院システム情報科学研究院
Author PID
K000171
Creator Name
Murakami, Kazuaki
村上, 和彰
ムラカミ, カズアキ
Affiliation
Affiliation Name
Graduate School of Information Science and Electrical Engineering, Department of Informatics, Kyushu University
九州大学大学院システム情報科学研究院
Language
English
Date
2009-06-08
Source Title
Workshop on Accelerators for High-performance Architectures
Source Title
SLRC Papers Database
Vol
1
Publication Type
Accepted Manuscript
Access Rights
open access
Related DOI
Workshop on Accelerators for High-performance Architectures || 1
http://www.ics-conference.org/index.html
http://www.slrc.kyushu-u.ac.jp/index-j.html
Related URI
Workshop on Accelerators for High-performance Architectures || 1
http://www.ics-conference.org/index.html
http://www.slrc.kyushu-u.ac.jp/index-j.html
Relation
Workshop on Accelerators for High-performance Architectures || 1
http://www.ics-conference.org/index.html
http://www.slrc.kyushu-u.ac.jp/index-j.html
Abstract A large-scale reconfigurable data-path (LSRDP) processor based on single-flux quantum circuits has been proposed to overcome the barriers originating from the CMOS technology. LSRDP is integrated to a... general purpose processor in a high-performance computing system to accelerate the execution of data flow graphs extracted from scientific applications. The LSRDP micro-architecture design procedure using a quantitative approach over benchmark data flow graphs and its specifications will be presented. A preliminary performance evaluation of the reconfigurable processor will be given in this paper as well.show more

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Details

Record ID
14876
Peer-Reviewed
Unrefereed
Notes
Workshop on Accelerators for High-Performance Architecture (WAHA) in Conjunction with 23rd International Conference on Supercomputing (ICS) : June 8-12, 2009 : IBM T.J. Watson Research Center, Yorktown Heights, NY, USA
Type
会議発表論文
Created Date 2009.06.24
Modified Date 2020.11.27

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