A Design of First-Order Delay-Line DPLL in 1.2μm CMOS Technology - Collections | Kyushu University Library

＜departmental bulletin paper＞
A Design of First-Order Delay-Line DPLL in 1.2μm CMOS Technology

Creator	Creator Name Seki, Ikuo セキ, イクオ Affiliation Affiliation Name Department of Electrical Enginering, Kyushu University : Graduate Student \| Toshiba, Co.
	Creator Name Nakashi, Kenichi ナカシ, ケンイチ Affiliation Affiliation Name Department of Electronic Device Engineering, Kyushu University
	Creator Name Ushida, Mitsuhiko ウシダ, ミツヒコ Affiliation Affiliation Name Department of Electrical Engineering, Kyushu University : Graduate Student \| Kawasaki Heavy Industry, Co.
	Creator Name Taniguchi, Kenji タニグチ, ケンジ Affiliation Affiliation Name Department of Electronic Device Engineering, Kyushu,University
Language	English
Publisher	九州大学大学院システム情報科学研究院
Publisher	Faculty of Information Science and Electrical Engineering, Kyushu University
Date	1996-09-27
Source Title	Research reports on information science and electrical engineering of Kyushu University
Vol	1
First Page	45
Last Page	50
Publication Type	Version of Record
Access Rights	open access
JaLC DOI	https://doi.org/10.15017/1474940
Related DOI	https://portal.isee.kyushu-u.ac.jp/
Related URI	https://portal.isee.kyushu-u.ac.jp/
Relation	https://portal.isee.kyushu-u.ac.jp/
Abstract	This paper describes a CMOS 1st-order delay-line DPLL in l.2μm technology for clock regeneration. We have employed a parallel-architecture PC (Phase Comparator) to improve the speed and a DCO (Digital...ly Controlled Oscillator) without timing hazard. And we have also laid it out in 1.2μm CMOS, and simulated its performance by SPICE as well as logic simulation. Results show that the DPLL operates up to 60MHz, and that lock-in ranges are +5/-5% for regular" 10" input and +5/-5% for 2^13-1 PRBS (Pseudo-Random Bit Sequence) input, respectively.show more

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PISSN	1342-3819
EISSN	2188-0891
NCID	AN10569524
Record ID	1474940
Peer-Reviewed	Refereed
Subject Terms	DPLL
	Delay-line
	CMOS
	Clock regeneration
	Parallel architecture
Created Date	2014.12.16
Modified Date	2020.11.17