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これまでに多くの低リーク・キャッシュが提案された．しかしながら，これらの手法は待機状態ラインのデータを破棄するため，ミス回数が増加し必然的に性能が低下する．そこで本稿では低リーク･キャッシュにおける性能低下抑制方式として，常活性ライン方式を提案する．具体的には，性能低下の原因となる待機状態ライン・アクセスの局所性を考慮し，アクセスが集中するラインは常活性ラインにする．これまでに提案されたCache... decay方式では，15.1%程度の性能低下をもたらす事で92.7%のリーク削減率を達成した．これに対し，本稿で提案する方式を適用すると，同程度のリーク削減率90.6%を維持しつつ，性能低下を5.0%に抑制することができた．
A number of techniques to reduce cache leakage energy have so far been proposed. However, in these techniques, flushing the data of a turning off line causes a new cache miss. And, the increase miss degrade processor performance. We have analyzed the detail of cache-access behavior, and have found that there is a locality of accesses to the turning-off lines. Based on this observation, we propose a cache management technique to alleviate the negative effect of low-leakage caches. In our approach, cache lines having high degree of increase-miss locality are forced to stay in the high-speed but high-leakage mode. In our evaluation, the proposed scheme worsens the performance by only 5.0% with the same degree of energy reduction of the Cache decay approach.show more
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