| 概要 |
In exploring ways to optimize Multiply and Accumulate (MAC) units, this study conducted a thorough experimental analysis focusing on four distinct signed multiplier architectures: Booth’s Multiplier (...BO), Modified Booth’s Multiplier (MBO), Vedic Multiplier (VM), Baugh-Wooley Multiplier (BA), and an advanced Baugh-Wooley Multiplier integrated with the Wallace Tree (BAW). Evaluations cover 8-bit, 16-bit, and 32-bit operations, scrutinizing critical performance metrics such as area utilization, power consumption, and critical path delay. A central theme of the study is integrating the Wallace Tree algorithm with the Baugh-Wooley Multiplier, which demonstrates significant enhancements in efficiency. This integrated approach reduces hardware requirements and achieves notable reductions in power consumption and critical path delay. These features make it particularly suitable for applications requiring robust and energy-efficient multiplier designs, such as those used in digital signal processing and embedded systems. Validation and analysis were rigorously conducted using the Xilinx tool on the Artix-7 AC701 Evaluation platform for delay and area, using the Cadence tool for power analysis, ensuring the reliability and relevance of the findings. The proposed Baugh-Wooley multiplier integrated with the Wallace tree structure results in approximately 60% reduced area, 70% decreased delay, and 73% lower power consumption in 32-bit multipliers. These impressive results position the Baugh-Wooley-Wallace combination as a promising advancement for MAC unit technologies, opening doors for further optimizations and practical applications. This study contributes significantly to the ongoing development of high-performance multiplier architectures tailored to meet contemporary computational demands.続きを見る
|
Mendeley出力
