Mendeley出力
＜図書＞
VLSI logic synthesis and design
| 責任表示 | edited by R.W. Dutton |
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| データ種別 | 図書 |
| 出版情報 | Tokyo : Ohmsha Amsterdam : IOS Press , c1991 |
| 本文言語 | 英語 |
| 大きさ | viii, 318 p. : ill. ; 27 cm |
| 概要 | Forty papers from the "Synthesis and simulation meeting and interchange" in Kyoto, October 1990, discuss recent developments in logic synthesis and design. The main topics include DSP layout, simulati...n, verification, and testing. Among the invited papers are treatments of formal hardware verification by symbolic simulation, test pattern generation using neural networks, and timing driven layout. No subject index. Available from IOS, PO Drawer 10558, Burke, VA 22009-0558. Annotation copyrighted by Book News, Inc., Portland, OR続きを見る |
所蔵情報
| 状態 | 巻次 | 所蔵場所 | 請求記号 | 刷年 | 文庫名称 | 資料番号 | コメント | 予約・取寄 | 複写申込 | 自動書庫 |
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: OHMSHA | 理系図2F 開架 | 549.7/D 99 | 1991 |
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031212008502317 |
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書誌詳細
| 一般注記 | Includes bibliographical references and index "This is the second Synthesis And Simulation Meeting and Interchange to be held in the Kansai" -- P. 1 |
|---|---|
| 著者標目 | Dutton, Robert W. |
| 分 類 | NDLC:M15 NDLC:ND |
| 書誌ID | 1001350066 |
| ISBN | 4274033120 |
| NCID | BA8721497X |
| 巻冊次 | : OHMSHA ; ISBN:4274033120 ; PRICE:9000円 : IOS Press ; ISBN:9051990464 |
| NBN | JP95054477 |
| 登録日 | 2009.09.18 |
| 更新日 | 2009.09.18 |