Mendeley出力
＜図書＞
Loop tiling for parallelism
| 責任表示 | Jingling Xue |
|---|---|
| シリーズ | The Kluwer international series in engineering and computer science ; SECS 575 |
| データ種別 | 図書 |
| 出版情報 | Dordrecht ; Boston : Kluwer Academic , c2000 |
| 本文言語 | 英語 |
| 大きさ | xix, 256 p. : ill. ; 25 cm |
| 概要 | For researchers and practitioners involved in optimizing compilers, and students in advanced computer architecture, Xue (computer science and engineering, U. of New South Wales, Australia) explores th... use of one of the most important compiler optimizations as it is used with parallel machines. He shows how it can reduce communications cost and improve parallelism for distributed memory machines. After providing mathematical foundations, he investigates loop permutability in the framework of non-singular loop transformations, discusses the necessary machineries required, and presents current results for finding tiling choices with the minimal communication and time. Each chapter includes references to the original literature. Annotation copyrighted by Book News, Inc., Portland, OR続きを見る |
所蔵情報
| 状態 | 巻次 | 所蔵場所 | 請求記号 | 刷年 | 文庫名称 | 資料番号 | コメント | 予約・取寄 | 複写申込 | 自動書庫 |
|---|---|---|---|---|---|---|---|---|---|---|
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理系図1F 開架 | 007.1/X | 2000 |
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026212000000545 |
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書誌詳細
| 一般注記 | Includes bibliographical references and index |
|---|---|
| 著者標目 | *Xue, Jingling |
| 書誌ID | 1001207927 |
| ISBN | 0792379330 |
| NCID | BA49092084 |
| 巻冊次 | ISBN:0792379330 |
| 登録日 | 2009.09.18 |
| 更新日 | 2009.09.18 |