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1.
雑誌論文
Kyushu Univ. Production 九州大学成果文献
Cover image of ハードウェア教育におけるFPGA導入の効果 — Educational Results of Hardware Course with FPGAs
澤田, 直; Sawada, Sunao; 富安, 洋史 ... [ほか]
出版情報: 九州大学大学院システム情報科学紀要. 4, (1), pp. 87-92, 1999-03-26. 九州大学大学院システム情報科学研究院
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概要: With the recent advances of integrated circuit technologies, very large systems can be implemented practically. It is strongly desired to educate students on the ability of VLSI design. KUE-CHIP2 is a simple 8-bit educational microprocessor with full control/observe facilities, which is useful to help students understand how microprocessor works. In Department of Electrical Engineering and Computer Science of Kyushu University, we have made a course of hardware design with KUE-CHIP2 bords since 1992. Undergraduate students design a KUE-CHIP2-compatible processor using schematic editer, and fabricate it using TTLs or FPGAs. In this paper, we will report the progress of the hardware experimental course. 続きを見る
2.
雑誌論文
Kyushu Univ. Production 九州大学成果文献
Cover image of 入力信号パターンを考慮した低電力算術演算回路の設計手法 — A Design Method for Low Power Arithmetic Circuits Considering Input Patterns
室山, 真徳; Muroyama, Masanori; 石原, 亨 ... [ほか]
出版情報: SLRC 論文データベース. 42, (4), pp. 1007-1015, 2001-04. 情報処理学会
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概要: 算術演算器はマイクロプロセッサをはじめ,画像処理などの様々なLSI の重要な構成要素である.ディジタル信号処理プロセッサ(DSP)や動画像 処理プロセッサでは並列乗算器の性能がシステム性能を左右する.算術演算 回路の設計においては1ビット全加算器(FA)やカウンタなどを基本セルと して用いて設計が行われる.本論文では,各基本セルへの入力信号パターン の偏りの影響を考えて,回路構造の異なる複数の基本セルの中から最も適し たセルを選択したり,セルの対称な入力端子への配線を変更したりすることで算術 演算回路の消費電力を削減する一手法を提案する.提案する手法により乗算 器の消費電力を32.1%削減できることを示し,回路の最適化手法も提示する. 続きを見る
3.
雑誌論文
Kyushu Univ. Production 九州大学成果文献
Cover image of Video Quality Modeling for Quality-driven Design
Cao, Yun; 曹, ユン; Yasuura, Hiroto ... [ほか]
出版情報: SLRC 論文データベース. pp. 86-92, 2001-10. Workshop on System And System Integration of Mixed Technologies
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概要: This paper models the video quality, which focuses on the effects of computation precision by combining subjective-objective metric. The motivation behind the research is to bring quality-driven design into effect for video applications. We change the computation-precision of IDCT, the kernel program of MPEG-2 video decoder and get the experimental computation-precision-oriented video quality model. The experimental results show that reducing computation precision while providing certain video quality is a perspective way to reduce cost for embedded system design. 続きを見る
4.
雑誌論文
Kyushu Univ. Production 九州大学成果文献
Cover image of Optimization of test accesses with a combined BIST and external test scheme
Sugihara, Makoto; 杉原, 真; Yasuura, Hiroto ... [ほか]
出版情報: SLRC 論文データベース. E84-A, (11), pp. 2614-2622, 2001-11. 電子情報通信学会
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概要: External pins for test are precious hardware resources because the number of them are strongly restricted. In this paper, an optimization method of test accesses with a combined BIST and external test (CBET) scheme is proposed. The method can minimizes test application time and eliminate the wasteful usage of external pins considering the trade-off between test application time and the number of external pins. Our ideas consist of two parts. One is to determine the optimum groups each of which consists of cores to simultaneously share mechanisms for external test. The other is to determine the optimum bandwidth of external input and output for external test. The ideas are basically used for the purpose of eliminating the wasteful external pin usage. The ideas make external test part to be under full bandwidth of external pins under consideration of the trade-off between test application time and the number of external pins. This is achieved only with CBET scheme because CBET permits test sets for both BIST and external test to be elastic. Taking test bus architecture for instance, a formulation for minimization of test application time and experimental results are shown. Experimental results shows that our optimization can achieve a 51.9% reduction of test application time of conventional test scheduling and our proposals are surely very effective to reduce test application time of SOC. 続きを見る
5.
雑誌論文
Kyushu Univ. Production 九州大学成果文献
Cover image of システムLSIの産業基盤構造に与えるインパクト — Impacts of System LSIs for Industrial Infrastructure
安浦, 寛人 ; Yasuura, Hiroto
出版情報: SLRC 論文データベース. 40, (12), pp. 872-878, 2001-12. 計測自動制御学会
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概要: 新しい情報化社会および産業の基盤を形成する基盤情 報技術として,ネットワーク技術,システムLSI 技術,ソフト ウェア技術が重要になっている.電子商取引などの経済 活動,電子政府や交通・通信・エネルギー産業などの社 会基盤,商工業や農業への応用など各種産業基盤に対 するシステムLSI の応用と基本的な設計技術の確立が求 められている.本稿では,情報の獲得(センサ技術),情 報の処理と蓄積(計算とメモリ技術),情報の伝達と通信 (表示と通信技術)を融合して半導体集積回路上に情報 システムを構築する技術としてシステムLSI を捉え,その 技術的,経済的特徴について考える.さらに,今後の基 盤情報技術として重要になると思われる財産,人命,プライバシなどにかかわる情報を取り扱う応用に対する設計技術の動向について議論する. 続きを見る
6.
雑誌論文
Kyushu Univ. Production 九州大学成果文献
Cover image of A Power Minimization Technique for Arithmetic Circuits by Cell Selection
Muroyama, Masanori; 室山, 真徳; Ishihara, Tohru ... [ほか]
出版情報: SLRC 論文データベース. 2002-01. 7th Asia South Pacific Design Automation Conference and 15th International Conference on VLSI Design
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概要: As a basic cell of arithmetic circuits, a one-bit full adder and a counter are usually used. Minimizing power consumption of these components is a key issue for low-power circuit design. This paper proposes a new design method, in which basic cells are selected from a set of circuits with different structures (symmetrical and asymmetrical) and connections to their terminals are exchanged, according to input-patterns to minimize power consumption. Experimental results for a parallel multiplier demonstrate average 30% power reduction. 続きを見る
7.
雑誌論文
Kyushu Univ. Production 九州大学成果文献
Cover image of Optimization of Test Accesses with a Combined BIST and External Test Scheme
Sugihara, Makoto; 杉原, 真; Yasuura, Hiroto ... [ほか]
出版情報: SLRC 論文データベース. pp. 683-688, 2002-01. IEEE Computer Society
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概要: External pins for test are precious hardware resources because this number is strongly restricted. Cores are tested via test access mechanisms (TAMs) such as a test bus architecture. When cores are tested via test buses which have constant bit widths, test stimuli and test responses for a particular core have to be transported over these test buses. The core might require more widths for input and output than test buses, and hence, for some part of the test, the TAMs are idle; this is a wasteful usage of the TAMs. In this paper, an optimization method of test accesses with a combined BIST and external test (CBET) scheme is proposed for eliminating the wasteful usage of test buses. This method can minimize the test time and eliminate the wasteful usage of external pins by considering the trade-off between test time and the number of external pins. Our idea consists of two parts. One is to determine the optimum groups, each of which consists of cores, to simultaneously share mechanisms for the external test. The other is to determine the optimum bandwidth of the external input and output for the external test. Our idea is basically formulated for the purpose of eliminating the wasteful external pin usage. We make the external test part to be under the full bandwidth of external pins by considering the trade-off between the test time and the number of external pins. This is achieved only with the CBET scheme because it permits test sets for both the BIST and the external test to be elastic. Taking test bus architecture as an example, a formulation for test access optimization and experimental results are shown. Experimental results reveal that our optimization can achieve a 51.9% reduction in the test time of conventional test scheduling and our proposals are confirmed to be effective in reducing the test time of system-on-a-chip. 続きを見る
8.
雑誌論文
Kyushu Univ. Production 九州大学成果文献
Cover image of 面積削減を目的としたデータ圧縮手法 — A Code Compression Technique for Chip Area Minimazation
門前, 淳; Monzen, Atsushi; 大隈, 孝憲 ... [ほか]
出版情報: SLRC 論文データベース. pp. 17-21, 2002-03. 電子情報通信学会ICD研究会
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概要: 本稿では,組み込みシステムにおける命令ROMの面積削減を目的としたオブジェクトコードの圧縮手法を提案す る.文字列圧縮法であるByte Pair 符号化はアルゴリズムがシンプルであり,任意の場所から展開ができる性質を持つ.命 令ROMを圧縮するための要求をピックアップし,より効率的に命令ROM を圧縮・展開できるようByte Pair 符号化を拡 張した.Byte Pair 符号化を使ったオブジェクトコード圧縮の実験をし,ROM 面積の削減に効果があることを確認した. 続きを見る
9.
雑誌論文
Kyushu Univ. Production 九州大学成果文献
Cover image of An Efficient Exploration Scheme for Datapath Width Optimization of Embedded Processor Systems
Mesbah, Uddin M.; Cao, Yun; 曹, ユン ... [ほか]
出版情報: SLRC 論文データベース. pp. 10-16, 2002-03. 電子情報通信学会VLD研究会
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概要: Datapath width optimization is very effective for designing a custom-made processor system with low cost and less power/energy consumption. However, to determine an optimal value of datapath width, designers need to iteratively work on a number of customizations which results in a long design time. In order to reduce design time, we propose an efficient scheme for reducing the design exploration space for the optimization. Through a single-pass simulation for a reference customization and a model for estimating and evaluating performance, reduction in design exploration space can be achieved. Experimental results show that substantial reduction in design exploration space is possible. 続きを見る
10.
雑誌論文
Kyushu Univ. Production 九州大学成果文献
Cover image of Low-Energy Memory Allocation and Assignment Based on Variable Analysis for Application-Specific Systems
Cao, Yun; 曹, ユン; Yasuura, Hiroto ... [ほか]
出版情報: SLRC 論文データベース. pp. 31-38, 2002-03. 電子情報通信学会VLD研究会
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概要: This paper presents a novel low-energy memory design technique based on variable analysis for on-chip data memory (RAM) in application-specific systems, which called VAbM technique. It targets the exploitation of both data locality and effective data width of variables to reduce energy consumed by data transfer and storage. Under constraints of the number of memory banks, VAbM technique use variable analysis results to perform allocating and assigning on-chip RAM into multiple banks, which have different size with different number of word lines and different number of bit lines tailored to each application requirements. Experimental results with several real embedded applications demonstrate significant energy reduction up to 64.8% over monolithic memory, and 27.7% compared to memory designed by banking technique. 続きを見る