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＜図書＞
Reconfigurable processor-array : a bit-sliced parallel computer

責任表示 Andrew Rushton
シリーズ Research monographs in parallel and distributed computing
データ種別 図書
出版者 London : Pitman
出版者 Cambridge, Mass : MIT Press
出版年 1989
本文言語 英語
大きさ 175 p. : ill ; 25 cm
概要 Processor arrays have established themselves as an inexpensive form of parallel computer suitable for a wide range of highly parallel applications. They achieve their performance by huge replication o... simple processors known as processing elements or PE. This book investigates enhancements to the conventional bit serial PE with the aim of improving its performance in situations where the small grain parallelism of a single instruction-stream, multiple data stream (SIMD) class parallel computer architecture is inefficient. The book describes the development of an SIMD class parallel computer based on processor arrays. Surprisingly, for many problems a large array of bit serial processing elements is a better source of processing power than a small array of complex processors, and the reconfigurable processor array described here is enhanced with floating-point, multiplication, and data cache facilities to improve the operation of such arrays. The RPA also has features that allow clusters of processing elements to operate on each data item so that hardware parallelism can be matched with data parallelism. The implementation of the architecture as a chip design, for possible VLSI realization, is described, and an appendix contains a high level formal description of the processing element in a registertransfer language. Andrew Rushton teaches at the University of Southampton. Reconfigurable Processor Array is included in the series Research Monographs in Parallel and Distributed Computing, copublished with Pitman Publishing.
Processor arrays have established themselves as an inexpensive form of parallel computer suitable for a wide range of highly parallel applications. They achieve their performance by huge replication of simple processors known as processing elements or PE. This book investigates enhancements to the conventional bit serial PE with the aim of improving its performance in situations where the small grain parallelism of a single instruction-stream, multiple data stream (SIMD) class parallel computer architecture is inefficient. The book describes the development of an SIMD class parallel computer based on processor arrays. Surprisingly, for many problems a large array of bit serial processing elements is a better source of processing power than a small array of complex processors, and the reconfigurable processor array described here is enhanced with floating-point, multiplication, and data cache facilities to improve the operation of such arrays. The RPA also has features that allow clusters of processing elements to operate on each data item so that hardware parallelism can be matched with data parallelism. The implementation of the architecture as a chip design, for possible VLSI realization, is described, and an appendix contains a high level formal description of the processing element in a registertransfer language. Andrew Rushton teaches at the University of Southampton. Reconfigurable Processor Array is included in the series Research Monographs in Parallel and Distributed Computing, copublished with Pitman Publishing. 続きを見る

所蔵情報


【故障中】理系図 自動書庫
1989
031212016500643
: pbk. 【故障中】理系図 自動書庫 007.64/R 21 1989
031212006505693

書誌詳細

一般注記 Bibliography: p151-160
著者標目 *Rushton, Andrew
件　名 PRECIS:Computer systems. Parallel-processor systems
LCSH:Parallel processing (Electronic computers)
分　類 LCC:QA76.6
DC19:004/.35
書誌ID 1001113298
ISBN 0273087991
NCID BA07638523
巻冊次 ISBN:0273087991 ; PRICE:£17.95 : CIP rev
: pbk. ; ISBN:0262680572
NBN B8842291
登録日 2009.09.17
更新日 2016.05.12

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