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| Abstract |
本稿では，高速かつ正確なキャッシュシミュレーション法について述べ，先行研究と定量的な比較を行い有効性を評価する．一般に，キャッシュメモリのシミュレーションにはトレース・ドリブン方式が用いられる．設計空間の拡大に伴い評価対象が増加しており，評価時間が長くなる傾向にある．トレース・サイズの削減によりシミュレーション時間を短縮できるが，精度が低下するという問題が生じる．そこで，本手法はメモリ・アクセスの...特徴を利用し，精度を維持しつつ時間の短縮を実現する．先行研究と比較した結果，トレース・サイズは平均81.7%削減され，キャッシュ・ミス率の予測精度は平均34.6%向上した．
This paper proposes a fast, accurate cache simulation technique for efficient design space exploration, and shows its efficiency by means of comparing with a related approach. Trace-driven simulation is a well known methodology to measure memory-system performance, e.g. cache hit rates. One of advantages of this method is the high-speed of simulations. Since the trend increases the complexity of microprocessor chips, e.g. CMPs, however, it is strongly required to achieve much faster simulations without sacrificing the accuracy of performance prediction. The proposed approach first attempts to characterize the memory-access patters, and then generates a small but well-constructed memory-access trace as a stimulus of cache simulators. In our evaluation, it is observed that the proposed technique reduces the trace size by 81.7% while the accuracy of cache miss rates is improved by 34.6%, compared with SimPoint approach.show more
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