An On-chip Memory-Path Architecture on Merged DRAM/Logic LSIs for High-Performance/Log-Energy Consumption - Collections

＜conference paper＞
An On-chip Memory-Path Architecture on Merged DRAM/Logic LSIs for High-Performance/Log-Energy Consumption

Creator	Author PID K002613 Creator Name Inoue, Koji 井上, 弘士イノウエ, コウジ Affiliation Affiliation Name Department of Computer Science and Communication Engineering, Kyusyu University 九州大学大学院システム情報科学研究科情報工学専攻
	Creator Name Kai, Koji 甲斐, 康司カイ, コウジ Affiliation Affiliation Name Institute of Systems and Information Technologies/Kyushu 九州システム情報技術研究所
	Author PID K000171 Creator Name Murakami, Kazuaki 村上, 和彰ムラカミ, カズアキ Affiliation Affiliation Name Department of Computer Science and Communication Engineering, Kyusyu University 九州大学大学院システム情報科学研究科情報工学専攻
Language	English
Date	2000-04
Source Title	Proceedings of International Symposium on Low-Power and High-Speed Chips (COOL Chips III)
Source Title	SLRC Papers Database
First Page	283
Last Page	283
Publication Type	Accepted Manuscript
Access Rights	open access
Related DOI	Proceedings of International Symposium on Low-Power and High-Speed Chips (COOL Chips III) \|\| \|\| p283
Related DOI	http://www.c.csce.kyushu-u.ac.jp/SOC/index_j.html
Related URI	Proceedings of International Symposium on Low-Power and High-Speed Chips (COOL Chips III) \|\| \|\| p283
Related URI	http://www.c.csce.kyushu-u.ac.jp/SOC/index_j.html
Relation	Proceedings of International Symposium on Low-Power and High-Speed Chips (COOL Chips III) \|\| \|\| p283
Relation	http://www.c.csce.kyushu-u.ac.jp/SOC/index_j.html

File	FileType	Size	Views	Description
Inoue2	pdf	74.6 KB	177

Record ID	7346
Peer-Reviewed	Unrefereed
Subject Terms	merged DRAM/logic LSI
Subject Terms	DRAM/ロジック混載LSI
Notes	International Symposium on Low-Power and High-Speed Chips (COOL Chips III) : April 24-25, 2000 : Tokyo
Type	会議発表論文
Created Date	2009.04.22
Modified Date	2020.11.02