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Performance Balancing: Software-based On-chip Memory Management for Multicore Processors

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Abstract 本稿では,プログラムの特徴に応じてメモリ性能を改善するマルチコア・プロセッサ向けオンチッ プメモリ貸与法を提案し,評価を行った.マルチコア・プロセッサの性能向上阻害要因として,メモリウォール問題の顕著化がある.これに対して,一部のプロセッサコアを「演算用」だけでなく「メモリ性能向上用」に活用することで,性能向上ならびに消費エネルギー削減を目指す.メモリ性能向上用のコアは,自身が持つオンチップメモリ...を演算用のコアへ貸与し,プログラム実行を行わない.プログラムの特徴に応じてメモリ性能向上用のコア数を変更することで,演算性能とメモリ性能の間の適切なバランスを取る.これにより,主記憶アクセス回数の削減による高性能化,ならびに,一部コアの動作停止による低消費エネルギー化を同時に狙う.提案手法をサポートするコンパイル手法を開発し,実機を用いた定量的な評価を行った結果,最大で46%の実行時間の削減と32%の消費エネルギーの削減を達成した.
This paper proposes the concept of performance balancing, and reports its performance and energy impact on a multicore processor. Integrating multiple processor cores into a single chip, can achieve higher peak performance by means of exploiting thread level parallelism. However, the off-chip memory bandwidth which does not scale with the number of cores tends to limit the potential of multicore processors. To solve this issue, the technique proposed in this paper attempts to make a good balance between computation and memorization. Unlike conventional parallel executions, this approach exploits some cores to improve the memory performance. These cores devote the on-chip memory hardware resources to the remaining cores executing the parallelized threads. In our evaluation, it is observed that our approach can achieve 46% of reducing execution time and 32% of reducing energy compared to a conventional parallel execution model.
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Peer-Reviewed
Created Date 2011.01.14
Modified Date 2020.11.27

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