Performance Balancing: Software-based On-chip Memory Management for Effective CMP Executions - Collections

＜conference paper＞
Performance Balancing: Software-based On-chip Memory Management for Effective CMP Executions

Creator	Author PID L001453 Creator Name Fukumoto, Naoto 福本, 尚人フクモト, ナオト Affiliation Affiliation Name Department of Advanced Information Technology, Kyushu University 九州大学大学院システム情報科学研究院情報知能工学部門
	Author PID L002065 Creator Name Imazato, Kenichi 今里, 賢一イマザト, ケンイチ Affiliation Affiliation Name Department of Advanced Information Technology, Kyushu University 九州大学大学院システム情報科学研究院情報知能工学部門
	Creator Name Inoue, Koji 井上, 弘士イノウエ, コウジ Affiliation Affiliation Name Department of Advanced Information Technology, Kyushu University 九州大学大学院システム情報科学研究院情報知能工学部門
	Author PID K000171 Creator Name Murakami, Kazuaki 村上, 和彰ムラカミ, カズアキ Affiliation Affiliation Name Department of Advanced Information Technology, Kyushu University 九州大学大学院システム情報科学研究院情報知能工学部門
Language	English
Publisher	ACM Press
Date	2009-09
Source Title	MEDEA2009
Source Title	SLRC Papers Database
First Page	28
Last Page	34
Publication Type	Accepted Manuscript
Access Rights	open access
Related DOI	MEDEA2009 \|\| p28-34
Related URI	MEDEA2009 \|\| p28-34
Relation	MEDEA2009 \|\| p28-34

File	FileType	Size	Views	Description
fukumoto09_1	pdf	243 KB	95

Record ID	18827
Peer-Reviewed	Unrefereed
Subject Terms	Chip MultiProcessors
	Scratchpad Memory
	Parallel Execution
	Memory-wall Problem
ISBN	978-1-60558-830-8
Notes	This paper proposes the concept of performance balancing, and reports its performance impact on a Chip multiprocessor (CMP). Integrating multiple processor cores into a single chip, or CMPs, can achieve higher peak performance by means of exploiting thread level parallelism. However, the off-chip memory bandwidth which does not scale with the number of cores tends to limit the potential of CMPs. To solve this issue, the technique proposed in this paper attempts to make a good balance between computation and memorization. Unlike conventional parallel executions, this approach exploits some cores to improve the memory performance. These cores devote the on-chip memory hardware resources to the remaining cores executing the parallelized threads. In our evaluation, it is observed that our approach can achieve 31% of performance improvement compared to a conventional parallel execution model.
Created Date	2011.01.14
Modified Date	2020.11.17