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A Dynamic Management Technique of a Non-uniform Selective Way Cache for Reducing the Energy Consumption of Embedded Processors

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Abstract 本稿はNon-uniform Selective Way Cache(NSWC) の動的ウェイ切り替えによる組込みプロセッサの省エネルギー化手法の提案を行う.NSWC は,消費エネルギーの観点で異なる性質の2種類のウェイを保持する.提案手法は命令キャッシュとしてNSWC を用い,アプリケーションプログラムへのウェイ切り替え命令を挿入することで,動的なウェイ切り替えを行う.動的ウェイ切り替えを行うこ...とで,キャッシュメモリのアクセスエネルギーの削減と高いキャッシュヒット率を両立し,組込みプロセッサの省エネルギー化を実現する.提案手法を用いることで,セット・アソシアティブ方式のキャッシュメモリを利用した場合と比較して7%~20%の消費エネルギー削減効果を確認した.
This paper proposes a dynamic management technique of Non-uniform Selective Way Cache(NSWC) for reducing the total energy consumption of a CPU core, cache memories, and off-chip memories. NSWC has a way uses low supply(Vdd) and low threshould(Vth). In our approach, we decide insert points of instructions to change available ways in the Non-uniform Selective Way Cache. Experiments using parameters of a commercial embedded processor and an off-chip SDRAM demonstrate that our algorithm reduces the energy consumption of the processor system by 7%-20% compared to the result of a processor with a same size set associative cache memory.
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Created Date 2009.04.22
Modified Date 2020.11.27

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